Etymology of MIPS

Raw extraction fields are retained for auditing. Their order does not establish ancestry.

{
  "templates": [
    {
      "name": "prefix",
      "args": {
        "1": "en",
        "2": "M",
        "3": "IPS",
        "gloss1": "mega-, 10⁶x"
      },
      "expansion": "M- (“mega-, 10⁶x”) + IPS"
    }
  ],
  "links": [
    [
      "M-",
      "M-#English"
    ],
    [
      "IPS",
      "IPS#English"
    ]
  ],
  "references": [],
  "descendants": [],
  "lexical": [
    {
      "pos": "name",
      "glosses": [
        "Initialism of Microprocessor without Interlocked Pipelined Stages, a RISC-style instruction set architecture."
      ],
      "tags": [
        "abbreviation",
        "alt-of",
        "initialism"
      ],
      "recordId": "daa4ac42af8eaec24a7f7dda9d3d1703655341577d90c695f2ed68fed922b61d",
      "rawRecordSha256": "dcdae866a17100abb8ebef4bbc862d1802a50a83f1748231f7679ae592b257b2",
      "sourceRecordOrdinal": 802679
    },
    {
      "pos": "noun",
      "glosses": [
        "Initialism of million instructions per second."
      ],
      "tags": [
        "abbreviation",
        "alt-of",
        "initialism",
        "plural",
        "plural-only"
      ],
      "recordId": "e9bf428cda8240b0024fba130c89f7e927c9fca7b2c19d00d1127481588acd0a",
      "rawRecordSha256": "6f57cf21a32247caaea4509a0056ecf9855ad8338887832a0e94307794a2ceca",
      "sourceRecordOrdinal": 802678
    }
  ],
  "omittedAuxiliaryFields": {
    "templates": 0,
    "links": 0,
    "references": 0,
    "descendants": 0,
    "lexicalRecords": 0,
    "lexicalSenses": 0,
    "glosses": 0
  }
}